Phase locked loop

November 5th, 2009 Ed Leave a comment Go to comments

PHASE  LOCK  LOOP

  

 

DPLL Image

DPLL Image

o       The PLL uses phase lock to perform its intended function.

o       Before phase lock can occurs it must have frequency lock.

o       After frequency lock has occurred, the phase comparator produces an output voltage that is proportional to the difference in the phase between the VCO output frequency and the external input frequency.

o       When there is no external input signal or when the feedback loop is open, the VCO operates at a preset frequency called its natural or free-running frequency (fn) .

o       The natural frequency is the VCO’s output frequency when the PLL is not lock.

 

Short for phase-locked loop, an electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. A PLL ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate and demodulate a signal and divide a frequency.

PLL is used often in wireless communications where the oscillator is usually at the receiver and the input signal is extracted from the signal received from the remote transmitter.

Digital PLL (DPLL)

 

Digital PLLs are a type of PLL used to sychronize digital signals. While DPLLs input and outputs are typically all digital, they do have internal functions which are dependent on analog signals. There are four basic components of a DPLL.

 

 
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