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XOR Gate Design and simulation by SPICE | Blinki Blog - 2 GB FREE
Home > Digital electronics > XOR Gate Design and simulation by SPICE

XOR Gate Design and simulation by SPICE

October 12th, 2010 admin Leave a comment Go to comments

The TG XOR gate

xor1

Program for TG XOR gate

* SPICE netlist written by S-Edit Win32 7.00

* Written on May 1, 2009 at 16:46:46

* Waveform probing commands

.probe

.options probefilename=”TG_xor.dat”

+ probesdbfile=”E:\education\Finalyear_Project\ULTIMATE\Gate\TGxor\TG_xor.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 B N20 Out GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 N1 A Out GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 Gnd B N1 GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M4 GND A N20 GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M5 B A Out VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M6 N1 N20 Out VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M7 N1 B VDD VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M8 N20 A Vdd VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v9 A GND bit({01} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v10 B GND bit({00} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

VDD VDD GND 1

.INCLUDE dual.md

.TRAN .1n 200n

.POWER VDD 100n 200n

.PRINT A B Out

.MEASURE tran Out trig v(A) val=0.5 rise=1 targ v(Out) val=0.5 rise=1

.END

* End of main circuit: Module0

Simulated output diagram

xor2

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