Home > Digital electronics > Nor gate:Design and simulation by SPICE

Nor gate:Design and simulation by SPICE

October 12th, 2010 admin Leave a comment Go to comments

Now let’s look at the other universal gate, i.e. the NOR gate. The design topology is almost similar to the NAND gate design, the only difference being the mode of connection between MOS in the pull-up and pull-down networks.

A NOR gate produces a low output when any of its inputs is high. Only when all of its inputs are low is the output high. A NOR gate, like the NAND gate, has another aspect of its operation that is inherent in the way it logically functions. We see that the high is produced at the output only and only if both the inputs are low. From this viewpoint, a NOR gate can be used for an AND operation that requires all low inputs to produce a high output. This aspect of NOR is called negative AND. The term negative in this context means that inputs are defined to be in the active or asserted state when low.

nor1Program for NOR gate simulation


* SPICE netlist written by S-Edit Win32 7.00

* Written on Apr 30, 2009 at 16:17:49

* Waveform probing commands

.probe

.options probefilename=”sedit.dat”

+ probesdbfile=”NOR.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 out B Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 out A Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 out B N2 Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M4 N2 A Vdd Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v5 B Gnd bit({0100} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v6 A Gnd bit({0101} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

Vdd Vdd Gnd 1

.INCLUDE dual.md

.TRAN .1n 200n

.POWER VDD 100n 200n

.PRINT tran A B out

.END

* End of main circuit: Module0

Simulated output diagram

nor2

  1. No comments yet.
  1. No trackbacks yet.
You must be logged in to post a comment.