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Design a NAND gate in SPICE and simulate | Blinki Blog - 2 GB FREE
Home > Digital electronics > Design a NAND gate in SPICE and simulate

Design a NAND gate in SPICE and simulate

October 12th, 2010 admin Leave a comment Go to comments

From the inverter, let’s move to the NAND gate. Being one of the universal gates, NAND gate holds utmost importance in any logic designnand1

Shown on the top is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

Program for NAND gate simulation

* SPICE netlist written by S-Edit Win32 7.00

* Written on Aug 30, 2008 at 11:36:09

* Waveform probing commands

.probe

.options probefilename=”Nand2.dat”

+ probesdbfile=”C:\Documents and Settings\Administrator\Desktop\udo\Nand2.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 outp b N2 Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 N2 a Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 outp a Vdd Vdd Ph L=.15u W=.45u AD=66p PD=2.4u AS=.3375p PS=2.4u

M4 outp b Vdd Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v5 b Gnd bit({01011} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v6 a Gnd bit({01101} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

vdd vdd gnd 1

.include dual.md

.tran .1n 800n

.power 100n 200n

.print tran a b outp

.END

* End of main circuit: Module0

Simulated output diagram

nand2

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