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CMOS:Power and switching

October 12th, 2010 admin Leave a comment Go to comments

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching (”dynamic power“). NMOS logic dissipates power whenever the output is low (”static power“), because there is a current path from Vdd to Vss through the load resistor and the n-type network.

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: P = CV2f.

A different form of power consumption became noticeable in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and  PMOS networks are partially conductive, and current flows directly from Vdd to Vss. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires has ameliorated this effect, and crowbar power is nearly always substantially smaller than switching power.

Both NMOS and PMOS transistors have a gate–source threshold voltage, below which the current through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V and Vth for both NMOS and PMOS might have been 700 mV). A special type of the CMOS transistor with near zero threshold voltage is the native transistor.

To speed up designs, manufacturers have switched to gate materials that lead to lower voltage thresholds. A modern NMOS transistor with a Vth of 200 mV has a significant sub thresh hold leakacge current. Designs (e.g. desktop processors) which try to optimize their fabrication processes for minimum power dissipation during operation have been lowering Vth so that leakage power begins to approximate switching power. As a result, these devices dissipate considerable power even when not switching. Leakage power reduction using new material and system design is critical to sustaining scaling of CMOS. The industry is contemplating the introduction of  high-k dielectrics to combat the increasing gate leakage current by replacing the silicon dioxide that is the conventional gate dielectric with materials having a higher dielectric constant.

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