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FET:Field effect transistor some questions

January 28th, 2011 admin No comments

Some questions i am asking and i am expecting some body to answer it or get the
answers from your teacher

Q1. Why it is called field effect?
Q2. What is the field mentioned here ,how the field mentioned here and is it related with the voltage
Q3. if related with the voltage with which voltage
Q4. What is our aim for studying the transistors
Q5. How FET transistors are different form those  of BJTS
Q6. Which one is better BJT or FET
Q7. In which application scenarios we use FET
Q8. What is unipolar and bipolar device
Q9. In FET Characteristic curve why after pinch-off the current saturates
Q10. What is the reason behind the saturation because as the channel get constricted then why current remain saturated
Q11. What are the applications where the saturation property of FET can be utilized.
Q12. What are the source and drain and how do we identify them though the device is a symmetrical device.
Q13. FET and MOSFET how they are different
Q14. FET and BJT which one consumes less power.

Now to answer those questions what bare things you need to read.

Must read the basic device of FET from any text book and then try to answer those.

Categories: Simple Electronics notes Tags:

Communication and Modulation

January 28th, 2011 admin No comments

INTRODUCTION TO COMMUNICATION

Telecommunication is the transmission of signals over a distance for the purpose of communication. In modern times, this process typically involves the sending of electromagnetic waves by electronic transmitters, but in earlier years it may have involved the use of smoke signals, drums or semaphore.

In a broadcast system, a central high-powered broadcast tower transmits a high-frequency electromagnetic wave to numerous low-powered receivers. The high-frequency wave sent by the tower is modulated with a signal containing visual or audio information. The antenna of the receiver is then tuned so as to pick up the high-frequency wave and a demodulator is used to retrieve the signal containing the visual or audio information. The information signal can be either analog (signal is varied continuously with respect to the information) or digital (information is encoded as a set of discrete signal values).

Basic elements: Each telecommunication system consists of three basic elements:

a transmitter that takes information and converts it to a transmit signal

a transmission medium over which the signal is transmitted

a receiver receives the transmit signal and converts it back into usable information

In this project only one way communication is taken into account. So this communication system falls under the category of Simplex.

Communication is simply the process of conveying message at a distance or communication is the basic process of exchanging information.

Information source produces required message which has to be transmitted.

Input transducer is a device which converts one form of energy to another form of energy. It converts information source output to a electrical signal.

What is Modulation:-

Modulation may be defined as a process by which some characteristics of a signal known as carrier is varied according to the instantaneous value of another signal known as modulating or base band signal. The signals containing intelligence or information to be transmitted are called the modulating signals. The carrier frequency is much greater than the base band signal frequency.

In the context of using antennas to radiate the transmitter output, modulation is used since we know that for efficient radiation

antenna height (l) = (wave length) / 4= velocity of light/(4*frequency).

That’s why modulation is done when audio frequency is transmitted using a radio frequency carrier in the MHz range, so antenna height is reduced.

Transmitter is used to modulate a carrier signal to produce a transmit signal.

Communication channel is the medium (e.g. optical fiber, free space etc.) through which the transmit signal travels from transmitter to receiver. Noise is unwanted signals which tend to interfere with the required signal.

Receiver reproduces the message signal in electrical form from noisy & distorted received signal.

Destination is the final stage which is used to convert an electrical message signal into its original form.


AM Transmitter A simple One with explanation

January 28th, 2011 admin No comments

Circuit Diagram

Circuit diagram

Working Principle

The improved Micropower AM Transmitter circuit has four sections as follows:

1. Crystal Oscillator Section

2. Audio Amplifier Section

3. Differential Amplifier Section

4. Antenna Matching Circuit

Each section is briefly described next.


Crystal Oscillator

A piezoelectric crystal such as quartz, exhibits electromechanical-resonance characteristics that are very stable and highly selective. The circuit symbol of crystal and its equivalent circuit is shown below.

The circuit of fig.(b) has two resonant frequencies.

A) Series resonant frequency ( fs )

B) Parallel resonant frequency ( fp )

The mathematical formulas given below

fs = ?s /2? = 1/(2??(LCs))

fp = (?p /2?)=(1/2?) ?( (Cp+ Cs) / LCpCs)

It is found that ?p > ?s as Cp >> CS. The reactance of the crystal is inductive over very narrow frequency band ?s & ?p . For a given crystal this frequency band is well defined .Thus we may use the crystal to replace the inductor of the Colpitts Oscillator.

In this circuit a Colpitts Oscillator is incorporated with crystal oscillator. The resulting circuit will oscillate at the resonance frequency of the crystal inductance L with the series equivalent of CS and Cp + {C1 C2 / (C1 + C2)}.

C1 & C2 are the 120 pF & 560 pF capacitors.

Since Cs is much smaller than the three other capacitance, it will be dominant and

?0 ~ 1 /?(LCs) = ?s

This oscillator circuit produces the carrier frequency of 1.8 MHz. We get this carrier frequency at the base of the Q1 transistor.

Audio Amplifier Section

In this section the audio signal is fed through the 10?F capacitor. Then this audio signal is fed to the base of the Q2 transistor. By the help of DC biasing, the transistor Q2 is kept in active region. This Q2 transistor amplifies the input audio signal & we get the amplified audio signal at the collector of the Q2. This collector point is connected to the common emitter point of the Differential Amplifier.

Differential Amplifier Section

In this section, transistors Q3 and Q4 comprise an emitter coupled differential amplifier. Here Q3 and Q4 are matched transistors forming a symmetric circuit. If we remove the audio signal then Q2 and corresponding biasing circuit will act as a constant current source. In DC bias condition if base voltages of Q3 & Q4 are equal (VCM) and if a constant current source is connected to the emitter of Q3 & Q4 then due to symmetry the current will divide equally between Q4 & Q3 and the common emitter point voltage will be almost VCM – VBE or (VCM - 0.7)V and the voltages of two collectors will be equal and the difference in voltage between collector is zero.

The gain of the differential amplifier is

Ad = -gm Rc [gm transconductance of Q1 & Q2 ]

The single ended gain is : Ad = - (1/2)gm Rc

The base of the Q4 is kept at a certain fixed voltage by proper dc biasing and the carrier signal of about 1.8MHz is given at the base of Q3 and the amplified output of the audio signal is fed to the common emitter point. Due to the varying emitter current at the audio rate, the transconductance varies at the audio rate affecting the gain. As a result, the amplitude of the carrier is varied according to the audio input signal and we get the amplified amplitude modulated wave at the output collector, which is fed to the matching circuit.

Antenna Matching Circuit

Antenna matching is very essential otherwise it may cause distortion in the transmitted signal. In this circuit the 0.1 ?F capacitor blocks the DC component and along with the variable capacitor ( 10 – 100 pF) it works as a matching circuit for the antenna. Here the 0.1 ?F capacitor is connected in series while variable capacitor is connected in parallel.

Applications:

  1. A continuous-loop tape could give sales information to passing cars. Place a sign that says, “tune to xxxAM for information,” next to the house or car that is for sale.

v Transmit special seasonal music at Christmas or Halloween to enhance your decorations. (Use a similar sign.)

2. Transmit a cassette player or other audio source to the car radio for better sound.

3. Make a pair of toy AM band two-way radios by adding inexpensive AM radios. Or talk between cars on a trip using the car radio for reception.

4.  Build a fully functional radio station for the kids - complete with vu meters, slide faders, and an “on the air” light.


Categories: Electronics project idea, News Tags:

XOR Gate Design and simulation by SPICE

October 12th, 2010 admin No comments

The TG XOR gate

xor1

Program for TG XOR gate

* SPICE netlist written by S-Edit Win32 7.00

* Written on May 1, 2009 at 16:46:46

* Waveform probing commands

.probe

.options probefilename=”TG_xor.dat”

+ probesdbfile=”E:\education\Finalyear_Project\ULTIMATE\Gate\TGxor\TG_xor.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 B N20 Out GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 N1 A Out GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 Gnd B N1 GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M4 GND A N20 GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M5 B A Out VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M6 N1 N20 Out VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M7 N1 B VDD VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M8 N20 A Vdd VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v9 A GND bit({01} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v10 B GND bit({00} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

VDD VDD GND 1

.INCLUDE dual.md

.TRAN .1n 200n

.POWER VDD 100n 200n

.PRINT A B Out

.MEASURE tran Out trig v(A) val=0.5 rise=1 targ v(Out) val=0.5 rise=1

.END

* End of main circuit: Module0

Simulated output diagram

xor2

Nor gate:Design and simulation by SPICE

October 12th, 2010 admin No comments

Now let’s look at the other universal gate, i.e. the NOR gate. The design topology is almost similar to the NAND gate design, the only difference being the mode of connection between MOS in the pull-up and pull-down networks.

A NOR gate produces a low output when any of its inputs is high. Only when all of its inputs are low is the output high. A NOR gate, like the NAND gate, has another aspect of its operation that is inherent in the way it logically functions. We see that the high is produced at the output only and only if both the inputs are low. From this viewpoint, a NOR gate can be used for an AND operation that requires all low inputs to produce a high output. This aspect of NOR is called negative AND. The term negative in this context means that inputs are defined to be in the active or asserted state when low.

nor1Program for NOR gate simulation


* SPICE netlist written by S-Edit Win32 7.00

* Written on Apr 30, 2009 at 16:17:49

* Waveform probing commands

.probe

.options probefilename=”sedit.dat”

+ probesdbfile=”NOR.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 out B Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 out A Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 out B N2 Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M4 N2 A Vdd Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v5 B Gnd bit({0100} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v6 A Gnd bit({0101} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

Vdd Vdd Gnd 1

.INCLUDE dual.md

.TRAN .1n 200n

.POWER VDD 100n 200n

.PRINT tran A B out

.END

* End of main circuit: Module0

Simulated output diagram

nor2

Design a NAND gate in SPICE and simulate

October 12th, 2010 admin No comments

From the inverter, let’s move to the NAND gate. Being one of the universal gates, NAND gate holds utmost importance in any logic designnand1

Shown on the top is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

Program for NAND gate simulation

* SPICE netlist written by S-Edit Win32 7.00

* Written on Aug 30, 2008 at 11:36:09

* Waveform probing commands

.probe

.options probefilename=”Nand2.dat”

+ probesdbfile=”C:\Documents and Settings\Administrator\Desktop\udo\Nand2.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 outp b N2 Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 N2 a Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 outp a Vdd Vdd Ph L=.15u W=.45u AD=66p PD=2.4u AS=.3375p PS=2.4u

M4 outp b Vdd Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v5 b Gnd bit({01011} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v6 a Gnd bit({01101} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

vdd vdd gnd 1

.include dual.md

.tran .1n 800n

.power 100n 200n

.print tran a b outp

.END

* End of main circuit: Module0

Simulated output diagram

nand2

Simulate an inverter using tanner Spice S-EDIT

October 12th, 2010 admin No comments

Program to simulate an inverter

* SPICE netlist written by S-Edit Win32 7.00

* Written on May 28, 2008 at 15:42:43

.probe

.options probefilename=”inver.dat”

+ probesdbfile=”C:\Documents and Settings\Administrator\Desktop\gr1\inver.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 b a Gnd Gnd Nh L=.15u W=.45u AD=66p PD=24u AS=66p PS=24u

M2 b a Vdd Vdd Ph L=.15u W=.9u AD=66p PD=24u AS=66p PS=24u

v3 a Gnd bit({01010101} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

vdd vdd gnd 1

.include dual.md

.tran .1n 800n

.power 100n 200n

.print tran a b

Simulated output diagram

sp1As can be seen from the waveform, the inversion of the input waveform has been achieved in the output waveform. So, the inverter characteristics are met.


The Inverter :How to design and Simulate

October 12th, 2010 admin No comments

Now we look at the simplest of gates: the NOT gate, or the inverter. The most popular method to build an inverter is using the static CMOS technology, and so we’re going to use that to see how much power consumption that particular architecture has.

CMOS circuits are constructed so that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance when a low voltage is applied to it and high resistance when a high voltage is applied to it. On the other hand, the composition of an NMOS transistor creates high resistance when a low voltage is applied to it and low resistance when a high voltage is applied to it.

inv1

The image on the top shows what happens when an input is connected to both a PMOS transistor and an NMOS transistor. When the voltage of input A is low, the NMOS transistor has high resistance so it stops voltage from leaking into ground, while the PMOS transistor has low resistance so it allows the voltage source to transfer voltage through the PMOS transistor to the output. The output would therefore register a high voltage.
On the other hand, when the voltage of input A is high, the PMOS transistor would have high resistance so it would block voltage source from the output, while the NMOS transistor would have low resistance allowing the output to drain to ground. This would result in the output registering a low voltage. In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output would be high, and when the input is high, the output would be low. Because of this, the CMOS circuits’ output is by default the inversion of the input.

Transmission Gates:How it operates

October 12th, 2010 admin No comments

A transmission gate is an electronic element. It is a good non-mechanical relay, built with CMOS technology. It is sometimes known as an analog gate, analogue switch or electronic relay depending on its use. It is made by the parallel combination of an nMOS and a pMOS transistor with the input at the gate of one transistor being complementary to the input at the gate    of the other.

tgate1

Operation:

A current can flow through this element in either direction. Depending on whether or not there is a voltage on the gate, the connection between the input and output is either low-resistance or high-resistance, respectively. Ron = 100 ohm and Roff > 5 megohm.

tgate2The operation can also be understood this way: when the gate input to the nMOS transistor is ‘0′, and the complementary ‘1′ is gate input to the pMOS, both are turned off. However when gate input to the nMOS is ‘1′ and its complementary ‘0′ is the gate input to the pMOS, both are turned on and passes any signal ‘1′ or ‘0′ equally well without degradation. The use of transmission gates eliminates the undesirable threshold voltage effects which give rise to loss of logic levels in pass-transistors.

The above logic was invented as a solution to problems of earlier CMOS logics. It enables certain logic functions to be implemented with fewer transistors than possible using other CMOS logic.

This logic can be used to design multiplexers.

Design

It would seem that a transmission gate could be constructed using simply a single pMOS or nMOS transistor. If only an individual nMOS transistor were to be used, and there was a high voltage out the OUT and a low voltage on the IN and we are trying to transmit the zero to the OUT, then the nMOS will drain some of the voltage but not all of it leaving the OUT somewhere in the ‘no mans’ voltage region of digital circuits. Adding the pMOS gate in parallel allows all the voltage to drain after the nMOS shuts off before all the voltage is drained. This also solves the problem when transmitting a high voltage to OUT.

CMOS:Power and switching

October 12th, 2010 admin No comments

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching (”dynamic power“). NMOS logic dissipates power whenever the output is low (”static power“), because there is a current path from Vdd to Vss through the load resistor and the n-type network.

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: P = CV2f.

A different form of power consumption became noticeable in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and  PMOS networks are partially conductive, and current flows directly from Vdd to Vss. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires has ameliorated this effect, and crowbar power is nearly always substantially smaller than switching power.

Both NMOS and PMOS transistors have a gate–source threshold voltage, below which the current through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V and Vth for both NMOS and PMOS might have been 700 mV). A special type of the CMOS transistor with near zero threshold voltage is the native transistor.

To speed up designs, manufacturers have switched to gate materials that lead to lower voltage thresholds. A modern NMOS transistor with a Vth of 200 mV has a significant sub thresh hold leakacge current. Designs (e.g. desktop processors) which try to optimize their fabrication processes for minimum power dissipation during operation have been lowering Vth so that leakage power begins to approximate switching power. As a result, these devices dissipate considerable power even when not switching. Leakage power reduction using new material and system design is critical to sustaining scaling of CMOS. The industry is contemplating the introduction of  high-k dielectrics to combat the increasing gate leakage current by replacing the silicon dioxide that is the conventional gate dielectric with materials having a higher dielectric constant.