See the figure and I will explain that to you.
First initially the SR Flip flop is in RESET state. Those who donot know what a flip flop is just keep remembering that it has 2 inputs named S and R and two outputs named as Q and Q_bar.If Q is HIGh then Q_BAR is low and vice versa. Note. Whan S=1 R=0 Then Q=HIGH and when S=0,R=1 Then Flip flop is in reset state. And When S=0,R=0 Then it is in no change state and Q and Q_bar value remains at it was earlier for other values of S and R. Here S-R kind of flip flop is being used.
So initially the flip flop is in reset state that means Q=LOW and the output of the Flip flop may be thought as HIGH ,another thing need to remember is that The trigger PIN is initially kept at a voltage higher than the VTL. So when the situation is like this then as VTH=2/3VCC and VTL=1/3VCC(because of the voltage divider network –voltage VCC is divided in three parts by using 3 equal registers).So What is the output of comparator1 :It is LOW.Why ?Because as Q is LOW so the Q_Bar is HIGH and this turns ON the transistor and as the point C is connected with the collector of the transistor so the voltage is zero there. Now consider the comparator 1 output ,it has Voltage LOW at +ve terminal than the voltage at the –ve terminal so output is LOW. For comparator 2 as the –ve terminal is maintained at a voltage more than VTL so the output is also LOW. So what we got –the outputs of the both comparators are low-So SR flip flop state remains unchanged –that means output will be at stable stage LOW.
What happens when we apply a trigger:
When we apply a trigger at the trigger terminal having pulse height lesser than VTL then output of comparator 2 is HIGH and output of comparator 1 is LOW, So this combination of S and R will set the flip-flop and so the output is HIGH now. So Q_bar is LOW and then and transistor goes OFF. So this way we reached at Quasi-stable state from the stable state.
How long to stay at Quasi-stable state ?
Now when it goes to quasi-stable state then as point C is no longer connected to ground via the transistor as transistor is OFF NOW so the capacitor begins charging so voltage at point C go on increasing ,as the capacitor will try to charge towards VCC so a time will come when the voltage at point C will exceed the VTH , Then the output of the comparator1 will go HIGH and the comparator 2 has LOW output because triggering pulse gone. So this is the RESET condition and the Flip flop will reset and the Q=LOW again. Q_bar is HIGH and transistor will be ON and then voltage at point C will now go towards zero after discharge of the charge capacitor stored the voltage at C is completely zero and so recovery done and multivibrator is aging at the stable state LOW.