In digital electronics, different logics are implemented through different, separate circuits named logic gates. Over the course of development of transistors, extensive research has been made in implementation of gates efficiently by them. Not much after, CMOS technology was in the horizon and due to their low power consumption and other benefits over the regular transistors, we chose the MOS to create logical circuits according to our needs. Today, most of the logic circuits we use or come face to face with in our daily life as well as research are made of CMOS. In recent years, Transmission Gate (Commonly abbreviated as TG) has taken over the realm of logic gate design over the plain depletion mode or enhancement mode MOSFETs; but the TG technology isn’t all pro and no con. Though it has significant improvements over the common CMOS in space requirements and faster operation, it loses out primarily on power consumption. So, the newest addition to this field of logic gate implementation has been the introduction of hybrid architecture, one which has the benefits of both the CMOS and the Transmission gates. In this particular segment of the project, we will design several logic gates with normal CMOS, normal TG and hybrid architectures, and compare them on different parameters. Our focus, though, would mainly be to design logic gates which are less power consuming, while being fastest amongst all the possible architectures. In the next section, some knowledge about power, delay and transistor counts of different models and how designers account it when designing adders/logic gates. In later section, we represent the implementation of different logic gates built with different logic designs: CMOS, TG-CMOS and Hybrid logic. Lastly, comparison in delay and power of different designs are given.