XOR Gate Design and simulation by SPICE

The TG XOR gate


Program for TG XOR gate

* SPICE netlist written by S-Edit Win32 7.00

* Written on May 1, 2009 at 16:46:46

* Waveform probing commands


.options probefilename=”TG_xor.dat”

+ probesdbfile=”E:\education\Finalyear_Project\ULTIMATE\Gate\TGxor\TG_xor.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 B N20 Out GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 N1 A Out GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 Gnd B N1 GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M4 GND A N20 GND Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M5 B A Out VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M6 N1 N20 Out VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M7 N1 B VDD VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M8 N20 A Vdd VDD Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v9 A GND bit({01} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v10 B GND bit({00} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)


.INCLUDE dual.md

.TRAN .1n 200n

.POWER VDD 100n 200n


.MEASURE tran Out trig v(A) val=0.5 rise=1 targ v(Out) val=0.5 rise=1


* End of main circuit: Module0

Simulated output diagram


Nor gate:Design and simulation by SPICE

Now let’s look at the other universal gate, i.e. the NOR gate. The design topology is almost similar to the NAND gate design, the only difference being the mode of connection between MOS in the pull-up and pull-down networks.

A NOR gate produces a low output when any of its inputs is high. Only when all of its inputs are low is the output high. A NOR gate, like the NAND gate, has another aspect of its operation that is inherent in the way it logically functions. We see that the high is produced at the output only and only if both the inputs are low. From this viewpoint, a NOR gate can be used for an AND operation that requires all low inputs to produce a high output. This aspect of NOR is called negative AND. The term negative in this context means that inputs are defined to be in the active or asserted state when low.

nor1Program for NOR gate simulation

* SPICE netlist written by S-Edit Win32 7.00

* Written on Apr 30, 2009 at 16:17:49

* Waveform probing commands


.options probefilename=”sedit.dat”

+ probesdbfile=”NOR.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 out B Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 out A Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 out B N2 Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M4 N2 A Vdd Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v5 B Gnd bit({0100} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v6 A Gnd bit({0101} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

Vdd Vdd Gnd 1

.INCLUDE dual.md

.TRAN .1n 200n

.POWER VDD 100n 200n

.PRINT tran A B out


* End of main circuit: Module0

Simulated output diagram


Design a NAND gate in SPICE and simulate

From the inverter, let’s move to the NAND gate. Being one of the universal gates, NAND gate holds utmost importance in any logic designnand1

Shown on the top is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

Program for NAND gate simulation

* SPICE netlist written by S-Edit Win32 7.00

* Written on Aug 30, 2008 at 11:36:09

* Waveform probing commands


.options probefilename=”Nand2.dat”

+ probesdbfile=”C:\Documents and Settings\Administrator\Desktop\udo\Nand2.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 outp b N2 Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M2 N2 a Gnd Gnd Nh L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

M3 outp a Vdd Vdd Ph L=.15u W=.45u AD=66p PD=2.4u AS=.3375p PS=2.4u

M4 outp b Vdd Vdd Ph L=.15u W=.45u AD=.3375p PD=2.4u AS=.3375p PS=2.4u

v5 b Gnd bit({01011} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

v6 a Gnd bit({01101} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

vdd vdd gnd 1

.include dual.md

.tran .1n 800n

.power 100n 200n

.print tran a b outp


* End of main circuit: Module0

Simulated output diagram


Simulate an inverter using tanner Spice S-EDIT

Program to simulate an inverter

* SPICE netlist written by S-Edit Win32 7.00

* Written on May 28, 2008 at 15:42:43


.options probefilename=”inver.dat”

+ probesdbfile=”C:\Documents and Settings\Administrator\Desktop\gr1\inver.sdb”

+ probetopmodule=”Module0″

* Main circuit: Module0

M1 b a Gnd Gnd Nh L=.15u W=.45u AD=66p PD=24u AS=66p PS=24u

M2 b a Vdd Vdd Ph L=.15u W=.9u AD=66p PD=24u AS=66p PS=24u

v3 a Gnd bit({01010101} pw=100n on=1.0 off=0.0 rt=.10n ft=.10n delay=0 lt=100n ht=100n)

vdd vdd gnd 1

.include dual.md

.tran .1n 800n

.power 100n 200n

.print tran a b

Simulated output diagram

sp1As can be seen from the waveform, the inversion of the input waveform has been achieved in the output waveform. So, the inverter characteristics are met.

The Inverter :How to design and Simulate

Now we look at the simplest of gates: the NOT gate, or the inverter. The most popular method to build an inverter is using the static CMOS technology, and so we’re going to use that to see how much power consumption that particular architecture has.

CMOS circuits are constructed so that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance when a low voltage is applied to it and high resistance when a high voltage is applied to it. On the other hand, the composition of an NMOS transistor creates high resistance when a low voltage is applied to it and low resistance when a high voltage is applied to it.


The image on the top shows what happens when an input is connected to both a PMOS transistor and an NMOS transistor. When the voltage of input A is low, the NMOS transistor has high resistance so it stops voltage from leaking into ground, while the PMOS transistor has low resistance so it allows the voltage source to transfer voltage through the PMOS transistor to the output. The output would therefore register a high voltage.
On the other hand, when the voltage of input A is high, the PMOS transistor would have high resistance so it would block voltage source from the output, while the NMOS transistor would have low resistance allowing the output to drain to ground. This would result in the output registering a low voltage. In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output would be high, and when the input is high, the output would be low. Because of this, the CMOS circuits’ output is by default the inversion of the input.

Transmission Gates:How it operates

A transmission gate is an electronic element. It is a good non-mechanical relay, built with CMOS technology. It is sometimes known as an analog gate, analogue switch or electronic relay depending on its use. It is made by the parallel combination of an nMOS and a pMOS transistor with the input at the gate of one transistor being complementary to the input at the gate    of the other.



A current can flow through this element in either direction. Depending on whether or not there is a voltage on the gate, the connection between the input and output is either low-resistance or high-resistance, respectively. Ron = 100 ohm and Roff > 5 megohm.

tgate2The operation can also be understood this way: when the gate input to the nMOS transistor is ‘0’, and the complementary ‘1’ is gate input to the pMOS, both are turned off. However when gate input to the nMOS is ‘1’ and its complementary ‘0’ is the gate input to the pMOS, both are turned on and passes any signal ‘1’ or ‘0’ equally well without degradation. The use of transmission gates eliminates the undesirable threshold voltage effects which give rise to loss of logic levels in pass-transistors.

The above logic was invented as a solution to problems of earlier CMOS logics. It enables certain logic functions to be implemented with fewer transistors than possible using other CMOS logic.

This logic can be used to design multiplexers.


It would seem that a transmission gate could be constructed using simply a single pMOS or nMOS transistor. If only an individual nMOS transistor were to be used, and there was a high voltage out the OUT and a low voltage on the IN and we are trying to transmit the zero to the OUT, then the nMOS will drain some of the voltage but not all of it leaving the OUT somewhere in the ‘no mans’ voltage region of digital circuits. Adding the pMOS gate in parallel allows all the voltage to drain after the nMOS shuts off before all the voltage is drained. This also solves the problem when transmitting a high voltage to OUT.

CMOS:Power and switching

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching (“dynamic power“). NMOS logic dissipates power whenever the output is low (“static power“), because there is a current path from Vdd to Vss through the load resistor and the n-type network.

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: P = CV2f.

A different form of power consumption became noticeable in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and  PMOS networks are partially conductive, and current flows directly from Vdd to Vss. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires has ameliorated this effect, and crowbar power is nearly always substantially smaller than switching power.

Both NMOS and PMOS transistors have a gate–source threshold voltage, below which the current through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V and Vth for both NMOS and PMOS might have been 700 mV). A special type of the CMOS transistor with near zero threshold voltage is the native transistor.

To speed up designs, manufacturers have switched to gate materials that lead to lower voltage thresholds. A modern NMOS transistor with a Vth of 200 mV has a significant sub thresh hold leakacge current. Designs (e.g. desktop processors) which try to optimize their fabrication processes for minimum power dissipation during operation have been lowering Vth so that leakage power begins to approximate switching power. As a result, these devices dissipate considerable power even when not switching. Leakage power reduction using new material and system design is critical to sustaining scaling of CMOS. The industry is contemplating the introduction of  high-k dielectrics to combat the increasing gate leakage current by replacing the silicon dioxide that is the conventional gate dielectric with materials having a higher dielectric constant.

CMOS Logic : an introduction:what is CMOS logic

Complementary metal–oxide–semiconductor (CMOS) , is a major class of integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication. Frank Wanlass successfully patented CMOS in 1967 (US Patent 3,356,858).

CMOS was also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or COS-MOS). The words “complementary-symmetry” refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.

Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices. CMOS also allows a high density of logic functions on a chip.

The phrase “metal–oxide–semiconductor” is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminum was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process, as announced by IBM and Intel for the 90 nanometer node and beyond.

“CMOS” refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power when static, and is denser than other implementations having the same functionality. As this advantage has grown and become more important, CMOS processes and variants have come to dominate, so that the vast majority of modern integrated circuit manufacturing is on CMOS processes.

CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications equipment, and signal processing equipment. Although CMOS logic can be implemented with discrete devices (for instance, in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions (or hundreds of millions) of transistors of both types on a rectangular piece of silicon of between 0.1 and 4 square centimeters. These devices are commonly called “chips”, although within the industry they are also referred to as “die” (singular) or “dice”, “dies”, or “die” (plural).

Logic Gates:Introduction

A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits. Logic gates are primarily implemented electronically using diodes or transistors, but can also be constructed using electromagnetic relays, fluidics, optics, molecules, or even mechanical elements.

In electronic logic, a logic level is represented by a voltage or current, (which depends on the type of electronic logic in use). Each logic gate requires power so that it can source and sink currents to achieve the correct output voltage. In logic circuit diagrams the power is not shown, but in a full electronic schematic, power connections are required.

The simplest form of electronic logic is diode logic. This allows AND and OR gates to be built, but not inverters, and so is an incomplete form of logic. Further, without some kind of amplification it is not possible to have such basic logic operations cascaded as required for more complex logic functions. To build a functionally complete logic system, relays, valves (vacuum tubes), or transistors can be used. The simplest family of logic gates using bipolar transistors is called resistor-transistor logic, or RTL. Unlike diode logic gates, RTL gates can be cascaded indefinitely to produce more complex logic functions. These gates were used in early integrated circuits. For higher speed, the resistors used in RTL were replaced by diodes, leading to diode-transistor logic, or DTL. It was then discovered that one transistor could do the job of two diodes in the space of one diode even better, by more quickly switching off the following stage, so transistor-transistor logic, or TTL, was created. In virtually every type of contemporary chip implementation of digital systems, the bipolar transistors have been replaced by complementary field-effect transistors (MOSFETs) to reduce size and power consumption still further, thereby resulting in complementary metal–oxide–semiconductor (CMOS) logic.

For small-scale logic, designers now use pre fabricated logic gates from families of devices such as the TTL 7400 series by Texas Instruments and the CMOS 4000 series by RCA, and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by programmable logic devices, which allow designers to pack a large number of mixed logic gates into a single integrated circuit. The field-programmable nature of programmable logic devices such as FPGAs has removed the ‘hard’ property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed.

Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-gain voltage amplifier, which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate.

Another important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they are cascadable. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems of arbitrary complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered.

The output of one gate can only drive a finite number of inputs to other gates, a number called the ‘fan-out limit’. Also, there is always a delay, called the ‘propagation delay’, from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed circuits. Additional delay can be caused when a large number of inputs are connected to an output, due to the distributed capacitance of all the inputs and wiring and the finite amount of current that each output can provide.

NAND, NOR logic gates are the basic building block of logic gates, in that all other types of Boolean logic gates (i.e., AND, OR, NOT, XOR, XNOR) can be created from a suitable network of just NAND or just NOR gate(s). They can be built from relays or transistors, or any other technology that can create an inverter and a two-input AND or OR gate. Hence the NAND, NOR gates are called the universal gates.

Digital electronics to VLSI

In digital electronics, different logics are implemented through different, separate circuits named logic gates. Over the course of development of transistors, extensive research has been made in implementation of gates efficiently by them. Not much after, CMOS technology was in the horizon and due to their low power consumption and other benefits over the regular transistors, we chose the MOS to create logical circuits according to our needs. Today, most of the logic circuits we use or come face to face with in our daily life as well as research are made of CMOS. In recent years, Transmission Gate (Commonly abbreviated as TG) has taken over the realm of logic gate design over the plain depletion mode or enhancement mode MOSFETs; but the TG technology isn’t all pro and no con. Though it has significant improvements over the common CMOS in space requirements and faster operation, it loses out primarily on power consumption. So, the newest addition to this field of logic gate implementation has been the introduction of hybrid architecture, one which has the benefits of both the CMOS and the Transmission gates. In this particular segment of the project, we will design several logic gates with normal CMOS, normal TG and hybrid architectures, and compare them on different parameters. Our focus, though, would mainly be to design logic gates which are less power consuming, while being fastest amongst all the possible architectures. In the next section, some knowledge about power, delay and transistor counts of different models and how designers account it when designing adders/logic gates. In later section, we represent the implementation of different logic gates built with different logic designs: CMOS, TG-CMOS and Hybrid logic. Lastly, comparison in delay and power of different designs are given.